Two independent trends in semiconductor technology, both with a long history contribute to the urgency for the present invention. The first trend concerns certain processes in the assembly of a semiconductor chip.
It is well known in semiconductor technology that bond pads on silicon integrated circuits can be damaged during wafer probing using fine-tip tungsten needles, further during conventional thermosonic wire bonding to aluminum metallization on the circuits, or during solder ball attachment in chip-to-substrate devices of more recent assembly developments. In wire bonding, particularly suspect are the mechanical loadings and ultrasonic stresses applied by the tip of the bonding capillary to the bond pad. When the damage is not apparent during the bonding process, the defects may manifest themselves subsequently by succumbing to thermo-mechanical stresses generated during the plastic encapsulation, accelerated reliability testing, temperature cycling, and device operation. The damage appears in most cases as microcracks which may progress to fatal fractures in the underlying dielectric material, as chip-outs of brittle or mechanically weak dielectric films, often together with pieces of metal or silicon, or as lifted ball bonds, or as delamination of metal layers.
Recent technological developments in the semiconductor industry tend to aggravate the problem. For instance, newer dielectric materials such as silicon-containing hydrogen silsesquioxane (HSQ) are being preferred due to their lower dielectric constant which helps to reduce the capacitance C in the RC time constant and thus allows higher circuit speed. Since lower density and porosity of dielectric films reduce the dielectric constant, films with these characteristics are introduced even when they are mechanically weaker. Films made of aerogels, organic polyimides, and parylenes fall into the same category. These materials are mechanically weaker than previous standard insulators such as the plasma-enhanced chemical vapor deposited dielectrics. This trend even affects stacks of dielectric layers such as alternating layers of plasma-generated tetraethylorthosilicate (TEOS) oxide and HSQ, or plasma-generated TEOS oxide and ozone-TEOS oxide (which is susceptible to failure much like HSQ). Since these material are also used under the bond pad metal, they magnify the risk of device failure by cracking.
In addition, the spacing between bond pads is being progressively reduced to save valuable silicon real estate. Consequently, the bonding parameters have to become more aggressive to achieve stronger bonds in spite of smaller size. Bonding force and ultrasonic energy during bonding are being increased. Again, the risk of yield loss and lowered reliability is becoming greater.
For conventional bond pad metallization processes, a solution to the aforementioned problems was disclosed in patent application Ser. No. 08/847,239, filed May 1, 1997, titled "System and Method for Reinforcing a Band Pad", assigned to Texas Instruments Incorporated. Some concepts and methods of this disclosure have been subsequently described in a publication entitled "Elimination of Bond-pad Damage through Structural Reinforcement of Intermetal Dielectrics" by M. Saran et al. (Internat. Reliab. Physics Symp., March 1998). In essence, a mechanically strong metal structure serves as a reinforcement for the mechanically weak dielectric layer. The metal is deposited and then etched to form "reservoirs" to be filled with the dielectric material, for example HSQ. For instance, the metal pattern thus formed may include grid-shaped or crucifix-shaped elements. The metal line widths and spacing are structured to confine much of the HSQ into the reservoirs while minimizing the area of each reservoir so that the HSQ layer is spared the direct mechanical impact of the bonding process.
Since HSQ is deposited by a spin-on process, the sizes of the reservoirs have to remain large enough to be filled controllably with the dielectric. This requirement is contrary to the industry trend for continued shrinking of all circuit feature sizes. Furthermore, the industry-wide trend towards smaller dimensions for increasing circuit speed brought the so-called damascene metallization process recently to wide acceptance. In this process flow, an insulator film is formed first; openings such as trenches are then etched into this film. Next, metal such as copper or aluminum is deposited to fill these openings. Whatever metal is deposited elsewhere on the surface, is removed by grinding and polishing, leaving only the metal embedded in the trenches. This process flow, however, is the inverse of the conventional process underlying the above cited patent application.
Wire bonding and solder ball flip-chip bonding over damascene metal pads are facing the same issues (transfer of mechanical and ultrasonic energies to the bond pads and risks of cracking weak dielectric layers) as in the case of conventional metallization. A patent disclosure titled "Fine-Pitch System and Method for Reinforcing Bond Pads in Semiconductor Devicee" (M. Saran et al., May 1998, assigned to Texas Instruments Incorporated) has been submitted for filing. It teaches the design and fabrication process for metal structures made with the damascene technique reinforcing weak dielectrics under the bond pads.
The second trend concerns aspects of manufacturing cost savings by conserving semiconductor "real estate". In order to accommodate balls of bonding wires or solder, typical bond pads on silicon integrated circuits have to be of appropriate size (typically ranging from squares of 80.times.80 .mu.m to squares of 150.times.150 .mu.m) and therefore consume an area between approximately 1 and 20% of the circuit area, dependent on the number of bond pads and the size of the integrated circuit. For manufacturing and assembly reasons, the bond pads are arranged in rows along the periphery of the circuit, usually stringed along all four chip sides.
Until now, all semiconductor devices manufactured had to exclude the area covered by the bond pads from use for laying out actual circuit patterns because of the high risk of damaging the circuit structures due to the unavoidable forces needed in the bonding process. Evidently, considerable savings of silicon real estate can be obtained if circuit patterns could be allowed to be laid out under the bond pad metal. One way to achieve this would be to create another level of metallization dedicated solely to bond pad formation. This level would be built over a protective overcoat covering an active circuit area. In existing technology, however, a special stress buffer layer of polyimide has to be applied between the protective overcoat and the extra metal layer, as shown by K. G. Heinen et al. ("Wire Bonds over Active Circuits", Proc. IEEE 44th Elect. Comp. Tech. Conf., 1994, pp. 922-928). The cost of applying this polyimide layer has so far prohibited the implementation of the bonds-over-active-circuit concept.
An urgent need has therefore arisen for a low-cost, reliable mass production system and method allowing the manufacture of wire and solder ball bonds directly over active integrated circuits areas. The system should provide stress-free, simple, and no-cost-added bond pads for flexible, tolerant bonding processes even when the bond pads are situated above one or more structurally and mechanically weak dielectric layers. The system and method should be applicable to a wide spectrum of design, material and process variations, leading to significant savings of silicon, as well as improved process yield and device reliability. Preferably, these innovations should be accomplished using the installed process and equipment base so that no investment in new manufacturing machines is needed.